Anritsu The MP1764D Error Detector is used in combination with the MP1763C Pulse Pattern Generator for 12.5G Bit Error Rate Testing to evaluate conformity with ITU-T standards. In addition, complicated searching for input thresholds or phase adjustments is simplified with the touch of a single key. These functions are ideally suited for the research and development of ultrahigh speed logic ICs and digital communication systems. This is the only 12.5G BERT system with differential inputs and º differential outputs required for SAN market device applications. In addition, this system supports 4.25G CDR for Fibre Channel applications. MP1764D is a version of the MP1764C 12.5G Error Detector that includes options for Differential Input (option MP1764C-02) and Variable CDR (option MP1764C-03). Features: Wide frequence range covers STM 0/STS1 to 10 GbE, STM64/STS192, OUT-2, and 4.25G Fibre Channel Differential Input option supports high speed differential signals used by XAUI and SFI-4P2 4-l